Service Overview
Service
Integration
IP Advisory & Procurement
Spec-in Service
Design Verification
Implementation
DFT
Ultra Low Power
High Performance
Mass Production
Package/System Test
QRA Ramp Acceleration
Process Yield Boost
Business Model
Chip Implementation
Physical design； Top level integration； IP subsystem；DFT
Mask Making & Wafer Processing
Substrate design & verification
Supply chain management
Packaging & Testing
Chip bring-up and debug
QA package design Test development
Product engineering
Logistics
Supply chain management
Logistic handling and delivery
Experienced Tape-out in Advanced Node
NTO Number (New Tape-out)
Integrated Turnkey Manufacturing Service
Complete Operation team to deliver Wafer, Package, Test and Production
Quality & Reliability
Supply Chain Management
Ship average >10kpcs of 12” wafer equivalent components per year
Test Engineeringy
Product Engineeringy
N7 and CoWoS package in volume production
Package Engineering
System Simulation y